1. Field of the Invention
The present invention relates to the manufacture and assembly of circuit boards for high pin count surface-mount pin-grid array integrated circuit packages. More particularly, the present invention relates to the circuit boards having a top surface layer adapted for soldering high pin count packages for high yield assembly operations.
2. The Prior Art
The quad flat package (QFP) is the most popular high pin count integrated circuit package currently in use. QFP's are rectangular in shape and have leads on all four peripheral sides of the package. The number of pins which can be provided on QFP packages depends on both the body size of the package and the pitch of the pins. A few illustrative packages of the QFP family and their associated pin density and pin count include: the QFP package, which is 40 mm.sup.2 in size and has either 232 pins at a pitch of 0.65 mm (25 mils), 300 pins at a pitch of 0.5 mm (20 mils), or 380 pins at a pitch of 0.4 mm (15 mils); the PGA package which is 58 mm.sup.2 in size, having 432 pins at a pitch of 2.54 mm (100 mils), or 34.5 mm.sup.2 in size, having 380 pins at a pitch of 1.27 mm (50 mils); and the SMPGA package, which is 34.5 mm.sup.2 in size, having 1024 pins at a pitch of 1 mm (40 mils). Because of the closeness of neighboring pins on these packages, a major drawback is the difficulty in surface mounting these devices. In addition, the pins are also very fragile and are easily bent, thus further complicating assembly processes employing them.
Packages with pin counts greater than 306 tend to be mostly pin grid array (PGA) packages. Most of these PGA packages are mounted to circuit boards using through-hole soldering techniques. A PGA package with pins at a 50 mil pitch has a higher pin density than any of the QFP's. The pin density of PGA packages with pins at 40 mil pitch is 3 times higher than the pin density of QFP's. Employing this type of integrated circuit package thus results in significant savings in circuit board area.
A major problem with soldering a 40 mil pitch through-hole package component is that the printed circuit board is almost impossible to make for this pitch for through-hole soldering. The primary constraint is that large holes (i.e., 20 mil minimum diameter) are required for through- soldering of the packages. A secondary design constraint is the metal trace width and the minimum space between traces. Fine pitch reduces the number of traces between vias, thereby contributing to increased circuit board thickness. The way to overcome these constraints is to use surface mount components such as surface-mount PGA packages. Connecting one layer to another on a surface mount board can be accomplished with vias as small as 10 mils. The smaller via dimensions allow more traces to pass between vias, thus further reducing overall pin pitch.
Printed circuit boards for surface mount pin grid arrays have been manufactured with conventional solder mask over bare copper (SMOBC) technology. Most printed circuit boards for these packages require multiple layers of metallization for routing. Multilayer printed circuit boards are fabricated by first patterning the internal layers on either single sided or double sided copper laminates. These laminates are then stacked with B-stage polymer separating the different layers. The stack is then laminated in a heated press. Holes are drilled and electroless copper plated to provide the interconnection between the different layers. Outerlayers are patterned. The vias and the outerlayers are then plated with electrolytic copper followed by solder. After the outerlayers have been patterned using the solder as a resist, the solder is stripped off. Liquid solder mask is then applied on areas where bonding is not going to be performed. The printed circuit board is then hot-air solder levelled(HASL) to coat the copper on the bonding pads with solder.
When surface mounting a surface mount pin grid array(SMPGA) device, solder paste is screened onto the bond pads. The component is then placed on top of the solder paste and the solder is reflowed. There are several problems with this manufacturing technique. The surface mount pin grid array leads form a butt joint. The strength of a butt joint is proportional to the height of the solder joint. The bond pad for 40 mil pitch and finer pitch pin grid arrays tends to be smaller than 24 mils on a side. In order to obtain a tall joint, a thick stencil capable of dispensing a 10 mil thick or thicker layer of solder paste has to be used. Such a thick layer of solder paste tends to droop and short neighboring pads together. The second problem is that if the via (which connects the pin to the inner layers) is very close, as is the case for these packages, the solder can flow down the via during the reflow operation. This will leave a smaller amount of solder to form the joint, causing, at best, the formation of a weak and unreliable joint and, at worst, an open solder joint.